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Espressif Systems /ESP32-P4 /LP_ADC /INT_ENA_W1TC

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Interpret as INT_ENA_W1TC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COCPU_SARADC1_INT_ENA_W1TC)COCPU_SARADC1_INT_ENA_W1TC 0 (COCPU_SARADC2_INT_ENA_W1TC)COCPU_SARADC2_INT_ENA_W1TC 0 (COCPU_SARADC1_ERROR_INT_ENA_W1TC)COCPU_SARADC1_ERROR_INT_ENA_W1TC 0 (COCPU_SARADC2_ERROR_INT_ENA_W1TC)COCPU_SARADC2_ERROR_INT_ENA_W1TC 0 (COCPU_SARADC1_WAKE_INT_ENA_W1TC)COCPU_SARADC1_WAKE_INT_ENA_W1TC 0 (COCPU_SARADC2_WAKE_INT_ENA_W1TC)COCPU_SARADC2_WAKE_INT_ENA_W1TC

Description

Interrupt enable deassert registers.

Fields

COCPU_SARADC1_INT_ENA_W1TC

ADC1 Conversion is done, write 1 to deassert int enable.
COCPU_SARADC2_INT_ENA_W1TC

ADC2 Conversion is done, write 1 to deassert int enable.
COCPU_SARADC1_ERROR_INT_ENA_W1TC

An errro occurs from ADC1, write 1 to deassert int enable.
COCPU_SARADC2_ERROR_INT_ENA_W1TC

An errro occurs from ADC2, write 1 to deassert int enable.
COCPU_SARADC1_WAKE_INT_ENA_W1TC

A wakeup event is triggered from ADC1, write 1 to deassert int enable.
COCPU_SARADC2_WAKE_INT_ENA_W1TC

A wakeup event is triggered from ADC2, write 1 to deassert int enable.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data